In the semiconductor industry, there is a continuing movement towards higher integration, density and production yield, all without sacrificing throughput or processing speed. The fabrication of integrated circuits (ICs) requires a complex process to ensure the proper balance between throughput, processing speed and yield. Inspections and tests are designed to detect unwanted variations in the wafers produced, as well as in the equipment and masks used in the fabrication processes. One small defect in either the devices produced or in the process itself can render a finished device inoperable.
Manufacturing ICs is a complex process that may involve hundreds of individual operations of fabrication, inspection and testing steps that are interwoven throughout the entire process. The fabrication process includes the diffusion of predetermined amounts of a dopant material into predetermined areas of a wafer, which is typically silicon, to produce active devices such as transistors. This is usually accomplished by forming a layer of silicon dioxide on the wafer, then utilizing a photomask and photoresist to define a pattern of areas into which diffusion occurs through a silicon dioxide mask. Openings are then etched through the silicon dioxide layer to define the pattern of precisely sized and located openings through which diffusion will take place. After a predetermined number of diffusion operations have been carried out to produce the desired number of transistors in the wafer, they are interconnected. Interconnection lines, or interconnects, are typically formed by deposition of an electrically conductive material that is formed into the desired interconnect pattern by a photomask, photoresist and/or etching process. Some high-performance ICs like the 1.3 GHz IBM Power4 microprocessor have hundreds of millions of transistors on a chip measuring 2 cm by 2 cm. Such chips include various devices disposed among 6 or 8 vertical layers and copper interconnects that total over a mile in length. Both devices and interconnects are measured in submicron dimensions.
In view of the device and interconnect densities required in current ICs, it is desirable that the manufacturing processes be carried out with utmost precision and in a manner that minimizes defects. In order to achieve reliable operation, the electrical characteristics of the circuits must be kept within carefully controlled limits, which require a high degree of control over all of the formation operations and fabrication processes. For example, in the photoresist and photomask operations, the presence of contaminants such as dust, minute scratches and other imperfections in the patterns on the photomasks can produce defective patterns on the semiconductor wafers, resulting in defective integrated circuits. Furthermore, defects can be introduced in the circuits during the diffusion operations themselves. Defective circuits may be identified by, for example, optical tools and electron-based tools. Various inspection tools offer different advantages (e.g., different resolution, different magnification, different wafer throughput). Typically, the smallest defects are inspected with SEM, or scanning electron microscopy. Optical diagnostic tools such as pico-second imaging circuit analysis, laser voltage probing, light-induced voltage alteration, optical beam induced current, Seebeck effect imaging, thermally-induced voltage alteration, and soft defect localization are becoming more common in IC chip fabrication. Once defective ICs have been identified, it is desirable to take steps to minimize the number of defective ICs produced in the manufacturing process, thus increasing the yield of non-defective ICs.
Defects are the primary killers of devices, wafers and circuits formed during manufacturing processes, resulting in yield losses. Increases in device density require smaller devices and interconnects, which appear to be approaching a physical limit of operability for certain such devices (i.e., field-effect transistors with channel layers several atomic layers thick). Defect detection in such atomic level devices becomes increasingly challenging. Specifically, it is more difficult to detect defects in individual devices or interconnects due to their smaller size, yet higher device density on a single chip means fewer total defects per chip are acceptable without causing chip failure. Many of the defects that cause poor yield in ICs were caused by particulate contaminants or other random sources. However, many of the defects seen in modem IC processes are not a result of particulates or random contaminants, but rather stem from systematic sources. Examples of systematic defect sources include printability problems from using aggressive lithography tools, poly stringers from improperly formed suicides, gate length variation from density driven and optical proximity effects. Other examples of defects include bubbles and particles in the photoresist layer of the IC. The diagnosis of defects in the photoresist layer can only be accomplished after the photoresist is developed. Furthermore, it is typically the case that the bubbles and particle defects in the photoresist do not appear as bubbles or particle defects after the photoresist is developed, but may take on some other distorted shape or appearance, further complicating the diagnosis.
In attempting to decrease the number of defective ICs produced in the manufacturing process, thereby increasing the yield, it is necessary to consider that any one or more of possibly several hundred processing steps may have caused a particular circuit to be defective. With such a large number of variables, it can be extremely difficult to determine the exact cause or causes of a defect or defects in a particular circuit thereby making it extraordinarily difficult to identify and correct yield reductions. While inspection of the completed ICs may provide some indication of which process operation may have caused the circuits to be defective, inspection equipment often does not capture many of the sources of systematic defects and/or the tools can be difficult to use effectively and reliably. Furthermore, inspection equipment may detect false defects, false alarms or nuisance defects that frustrate attempts to reliably detect true defects or sources of defects.
Once a particular cause of a true or catastrophic “killer” defect has been identified after completion of the fabrication process, it can be confirmed that a problem in a particular process operation was present at the time that the particular process operation was carried out, which could have been weeks or even months earlier. Thus, the problem might be corrected only after many defective ICs have been produced. By the time the first problem has been identified, other process operations may be causing problems. Thus, after-the-fact analysis of defective ICs and identification of process operations causing these defective products are of limited value to improve the overall yield of ICs.
What is needed to advance the state of the art is a method and apparatus of adaptive filtering of wafers and chips with chip design data within a semi-conductor fabrication process for accurate identification of catastrophic defects and accurate yield trends.